Today's deep submicron technologies allow the implementation of a huge amount of memory on a single chip. Typically, chips contain a large number of embedded small to medium size memories, e.g. SRAMs, and a few very large blocks, e.g. DRAMs. Due to their high density memories are more prone to faults. These memory faults decrease the total chip yield. One way to solve this problem is to enhance the memory by redundant memory locations or by a word redundancy. Word redundancy allows adding redundant registers to either a single SRAM block, or an SRAM block made up by more than one memory macros, with the possibility to detect the memory faults and activate the corresponding redundant memory locations to correct the memory faults on-line, during a memory test. Memories are tested either by external test hardware or by an on-chip dedicated hardware called a Memory Built-In Self Test (MBIST) which is the preferred approach for embedded memories. After the memory test, the information regarding the addresses of the memory faults is extracted from the chip and used to program associated on-chip laser fuses, which will permanently store this information.
FIG. 5 shows a prior art word oriented memory test structure for Built-in Self-Repair (BISR) of a RAM memory module 502, proposed by V. Schoeber, S. Paul, O. Picot, in “Memory Built-in Self-Repair using redundant words”, Proceedings of International Test Conference 2001, pp. 995–1001. The test structure comprises memory built-in self test (MBIST) logic 504 and redundancy logic 506 placed in parallel to the RAM memory module 502 to replace defect or failing memory words by redundant memory words. The test structure further comprises fuse boxes 508 including fuses to permanently store the addresses of failing memory words, a first multiplexer 510 in front of the RAM memory module 502, and a second multiplexer 512. The second multiplexer 512 is provided at the output of the RAM memory module 502 and the redundancy logic 506 and decides where to take the data from.
The MBIST logic 504 provides a read/write signal 514, a write data signal 516 and an address signal 518 to the first multiplexer 510 and a fail signal 520, a fail_address signal 522 and an expected_data signal 524 to the redundancy logic 506. The redundancy logic 506 receives the fail signal 520, the fail_address signal 522 and the expected_data signal 524 from the MBIST logic 504 and provides a data signal 526 and a control signal 528 to the second multiplexer 512. Furthermore, the redundancy logic 506 is connected to the fuse boxes 508 by a connection 530. The first multiplexer 510 receives the read/write signal 514, the write data signal 516 and the address signal 518 from the MBIST logic 504 and a data signal 532, an address signal 534 and a control signal 536 from e.g. a memory bus. The first multiplexer 510 comprises an output 538 connected to the redundancy logic 506 and the RAM memory module 502. The output 538 serves to either provide test patterns from the memory BIST logic 504 to the RAM memory module 502/redundancy logic 506 via the write data signal 516 or to provide data from e.g. a memory bus to the RAM memory module 502/redundancy logic 506 via the data signal 532. The second multiplexer 512 receives a data signal 540 from the RAM memory module 502 and the data signal 526 and the control signal 528 from the redundancy logic 506 and provides a data signal 542 of selected data.
FIG. 6 shows the prior art MBIST logic 504 of FIG. 5 in more detail. The MBIST logic 504 comprises an address register 544 and a write data register 546 for providing the address signal 518 and the write data signal 516 to the first multiplexer 510. The MBIST logic 504 additionally comprises a further address register 548 for storing the address of a failing memory location and for providing the fail_address signal 522, and a further data register 550 for storing the expected data and for providing the expected_data signal 524. The expected_data signal 524 is compared to the data signal 540 of the RAM memory module 502 after test data has been stored in a predetermined memory location under test via the write data signal 516. Therefore, the MBIST logic 504 further comprises a comparator 552 for comparing the expected data to the results of RAM data, that is, for comparing the data signal 540 of the RAM memory module 502 with the expected_data signal 524, and for providing a result 554 of the comparison. The MBIST logic 504 further includes a controller 556 for controlling a means 558 for providing the fail signal 520 in dependence of the result 554. The fail signal 520 is used to store data in the fuse boxes 508 and can be used as a write enable for the redundancy logic 506.
The data comes from MBIST logic 504 during test for each failing or defect memory word individually. An on chip memory test runs through the address space of the RAM memory module 502 and performs write and read operations in a given order, depending on the test algorithm. The memory output is compared to the expected data. If the memory words differ, part of the respective memory word is defect. In this case, the failing address and its data will be stored in the redundancy logic 506. Therfore the redundancy logic 506 comprises redundant or spare memory words arranged in an array of a plurality of redundant word lines and control logic to program the address decoding.
FIG. 7 shows one redundant memory word or redundant word line of a plurality of word lines contained in the redundancy logic 506 of FIG. 1. The redundant word line 560 includes a FA register 562, an address register 564, a data register 566, a comparator 568 and two AND gates 570, 572. If an address is stored in the address register 564 the FA register 562 is set to “1” to activate the redundant memory word. Then, the data register 566 is used for reading and writing instead of the RAM memory module 502. An address comparison is performed in the comparator 568. The address (A) 574 of an access to the entire memory space is compared to the address that is stored in the respective address registers 564 of redundant word lines. During test MBIST logic 504 prepares the fail signal 520, the fail_address signal 522, and the expected_data signal 524. A Read (R) 576, a Write (WR) 578, the Address (A) 574 and a data input (DI) 580 are accessed in parallel to the RAM memory module 502 and the redundancy logic 506 during functional operation and test. 582 (TDI) and 584 (TDO) are serial interfaces for the redundancy logic 506.
The programming of the failing addresses is done during the memory BIST or from the fuse boxes 508 during memory setup. Failing addresses that are stored in the address registers 564 of redundant word lines can be streamed out or read out after test completion to program the fuse boxes 508 by blowing fuses therein. To stream in and out data during test and redundancy configuration, the fuse boxes 508 can be connected via scan registers to the redundancy logic 506. In a fuse box multiple fuses and their scan register are placed in parallel. An additional fuse cell is necessary to activate a programmed address. The scan registers e.g. scan flip-flops are configured as a serial scan chain that can be activated during scan mode. The data output of the scan register is connected to the input of the fuse box. Fuse boxes can be placed inside or outside the redundancy logic 506 on-chip or off-chip to store identified failures after memory test. Fuses on-chip are state of the art. One fuse carries one address bit. The fuse itself is nothing more than a polysilicon or metal resistor, depending on technology. If the fuse boxes are placed outside of the redundancy logic 506 two configurations are possible. Parallel buses may connect the fuse boxes to the address registers of the redundant memory words. Instead of parallel access it is also possible to implement serial shift logic between the fuse boxes and the redundant memory words.
With the prior art test structure described above, if multiple functionally independent memories are present on a chip, a dedicated redundancy and test structure has to be provided for each memory. Therefore, a separate BIST controller and dedicated fuse boxes are needed for each memory increasing area overhead and test complexity. Furthermore, an efficient use of redundant words is impossible.